Thread: Amiga Vs ST
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Old 11 September 2014, 20:19   #479
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Originally Posted by Cyprian View Post
yep, ST-RAM is equivalent of CHIP RAM, where CPU can be a bit slowed down by e.g. HardDisk DMA channel or BLiTTER, and ALT-RAM is equivalent of Fastram.
You're confused. ST-RAM is not the equivalent of chipram.

On the ST, the "MMU" absolutely restricts the CPU (and later the STE blitter) to accessing memory on four CPU cycle boundaries. There are also large amounts of potential bandwidth that go unused during overscan and blanking.

On the Amiga these extra cycles are usable, for example by the blitter, or hardware sprites, or audio, and in some cases by the CPU.

This can make some blitter operations appear to come at no cost. A memory clear by the blitter during overscan is done almost for free with little CPU slowdown.

Chipram can also allow the CPU to access memory at times when ST-RAM would block the access.

          move.w (a0)+, d0 ; 8 cycles
          bne.s loop ; possibly 10 cycles on Amiga but always 12 cycles on ST
There are two internal CPU cycles at the beginning of the bne instruction if the branch is taken. This causes the first prefetch cycle of the bne instruction to fall on a cycle boundary that isn't a multiple of four. On the ST, this adds two wait states. But on the Amiga, if no other DMA is occurring, the CPU will not be made to wait.

This difference is small, admittedly, but it reduces the effect of the clock rate difference between the ST and Amiga.

In the above example, if the code runs during vertical overscan (in a Vblank int handler, for example), the ST will need to execute 20 cycles per loop while the Amiga will average slightly more than 18 cycles per loop.
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