Originally Posted by Schoenfeld
This is specific to the ACA SD-Ram design, because I'm doing a way faster burst than other 030 accelerators some 20 years ago: Back then, memories were not fast enough, and even with "keep the row open and cycle CAS line", you had to run one wait state to get the next data word on the bus.
My design runs 0-wait state after the first data word has been transferred. This speed was not possible 20 years ago, and I was confronted with a few problems of the 68030 that were not described anywhere. I found that the data setup and hold times must be very long before/after the data sample point, which gets more difficult if you have higher pin capacitance to drive.
If you run one more waitstate, you have 25ns more for data to settle, which is plenty, even with an FPU on the bus.
Nice work on giving your customers the FPU option (even if unsupported).
I mentioned (some time ago) using the FPU /Sense pin to detect the FPU and add a wait state to keep the SDRAM within specs. This should allow supported use of the FPU option (Unless, your just using a simple jumper to change /BERR to /FPUCS).
You might be surprised to know that 20 years ago, a 1 clock burst cycle was possible with the right DRAM controller. In fact, I'm currently using a 1 clock burst cycle on my DKB2632 but since it's running at 1/2 the 030's 54MHz clock speed it's a 2 clock burst from the 030's point of view.
20 years ago 60-70ns DRAMs were fast enough to support a 1 clock burst for most 030 accelerators (but most DRAM controllers didn't even try to support it).