Originally Posted by alenppc
Out of curiousity, is this specific to the ACA design? Would a (say) Blizzard 1230-IV suffer from the same problem?
This is specific to the ACA SD-Ram design, because I'm doing a way faster burst than other 030 accelerators some 20 years ago: Back then, memories were not fast enough, and even with "keep the row open and cycle CAS line", you had to run one wait state to get the next data word on the bus.
My design runs 0-wait state after the first data word has been transferred. This speed was not possible 20 years ago, and I was confronted with a few problems of the 68030 that were not described anywhere. I found that the data setup and hold times must be very long before/after the data sample point, which gets more difficult if you have higher pin capacitance to drive.
If you run one more waitstate, you have 25ns more for data to settle, which is plenty, even with an FPU on the bus.