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Old 22 August 2014, 23:52   #37
FPGAmiga rulez!
FrenchShark's Avatar
Join Date: Dec 2007
Location: South of France
Age: 43
Posts: 155
just my 2 cents about Cyclone III PLLs.
You can do 28.636363 MHz and 28.375 MHz if you use 5 MHz clock input.
5 x 227 / 40 = 28.375
5 x 252 / 44 = 28.636363
With PLL dynamic reconfiguration, you can switch between the two frequencies on the fly.
If you really look for cost saving, getting rid of the audio DAC is good. 3rd order delta-sigma in HDL gives good results. And you do not have to do sample rate conversion to 48, 96 or 192 KHz.
Another good cost saving is using active serial configuration on the cyclone III and the remote update feature. This way, you do not need the ARM chip.
With a 16 MB SPI Flash and FPGA bitstream compression, you can get 30+ different FPGA configuration.
BTW, did you use the 128Mb Flash with 64 KB sectors or 256KB sectors ?
IIRC, only the 256KB sectors one was compatible with Quartus II.
Best regards,

PS : I can see that your soldering skills are pretty good : 0402 and QFN components. Well done !
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