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Old 11 August 2014, 14:22   #33
Toni Wilen
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 43
Posts: 20,646
Originally Posted by phx View Post
Concerning P5_M68K_IPL:
These three bits are read-only and reflect the current IPL state on the mainboard. When an interrupt occurs, the PPC can read these bits to know which interrupt level it was.
P5_PPC_IPL is for masking interrupt levels on the PPC.
Can you confirm M68K_IPL bits only change when PPC CPU reads them? They seem to be stuck at all ones when M68K reads them, even inside interrupt routine.

Emulation does this and it seems to work.

Originally Posted by phx View Post
Confirmed! When I clear bit 0 of REG_LOCK on the 68k, then the PPC stops and continues working as soon as I set the bit. It also works from the PPC side. When setting it the 68k is stopped (which results in a system freeze, as PowerUp is controlled by 68k), but I verified that the PPC continues working after that.
Stops immediately or when it tries to do next memory access? (Maybe difficult to test, maybe by making sure test code is in instruction cache?)

Hmm. This is an A4000? Maybe there is a difference in the reset logic between the models.
Yes, desktop A4000. It just does that weird display blanking, nothing else.. (if P5_SELF_RESET is set to one)

I can try to do A3000 test but I am not sure if I am bothered to set correct jumpers..

P5_M68K_RESET and P5_PPC_RESET do not depend on P5_SELF_RESET
BPPC boot code also changes PPC_RESET without clearing P5_SELF_RESET.
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