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Old 06 August 2014, 12:24   #15
Toni Wilen
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 43
Posts: 20,651
Originally Posted by phx View Post
As you know everything which was publically known, and more by reengineering, there is probably nothing left I could help you with. But nevertheless I'm very curious to find out about every detail of the register set to document it.
Only way to continue is to try random things while PPC is active. (But I don't do PPC code). For example checking if clearing LOCK bit 0 triggers random interrupt or some other side-effect, or if it really needs strange 4*0x85 to IPL_EMU to "unlock" something..

This section reads quite confusing to me. Is the $f40000 address range you mentioned valid for BPPC, for CSPPC or only when SCSI is disabled? You wrote "also appear at": where does the flash primarily appear? I know that the CSPPC has some kind of ROM beginning at $f00000.
$f40000-$f4ffff is SCSI space. (f41000 to f42fff is RAM [no idea where this RAM comes from] for NCR SCSI SCRIPTS code. Interestingly SCRIPTS are not put in normal fast ram like most other NCR53c7xx based SCSI controllers store it)

$f50000-$f5ffff (and apparently also $f70000-$f7ffff) is something unknown, possibly related to memory controller configuration because boot rom code writes to all kinds of addreses in this space and after each write it does memory check. I assume it configures memory (SIMM) layout and boot code searches for memory layout that creates best memory space layout (due to different size SIMMs). Or something like that. This does not need emulating.

Can you give more details about the address ranges of the Flash?
Flash is linearly mapped from $f00000 to $f1ffff (CyberStorm, 128k flash) or $f00000 to $f3ffff + $f40000-$f5ffff when SCSI is disabled (BPPC, 512k flash)

f6xxxx is always board register io.

For the purpose of documentation, can you please repeat which are the enable-bits and which are the request-bits?
I'll recheck this first.
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