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Old 06 August 2014, 10:42   #14

phx's Avatar
Join Date: Nov 2009
Location: Herford / Germany
Posts: 1,058
As you know everything which was publically known, and more by reengineering, there is probably nothing left I could help you with. But nevertheless I'm very curious to find out about every detail of the register set to document it.

Originally Posted by Toni Wilen View Post
Also because BPPC has 512k flash (vs 128k in Cyberstorms), it has extra flash mapping, if SCSI is disabled (P5_SCSI_RESET is cleared), flash also appear at $f40000-$f5ffff, this space is mostly used, very tiny part at $f5c000 is used for config saving only. Apparently last 128k of flash is always unmapped. At least flash updater only writes first 384k of flash.
This section reads quite confusing to me. Is the $f40000 address range you mentioned valid for BPPC, for CSPPC or only when SCSI is disabled? You wrote "also appear at": where does the flash primarily appear? I know that the CSPPC has some kind of ROM beginning at $f00000.

Can you give more details about the address ranges of the Flash?

I forgot I renamed some registers because they looked wrong
My REG_IRQ = f60008.
Although it is as wrong as REG_ENABLE, when the register contains interrupt request and interrupt enable bits.

For the purpose of documentation, can you please repeat which are the enable-bits and which are the request-bits?
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