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Old 05 August 2014, 21:08   #10
phx
Natteravn

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Join Date: Nov 2009
Location: Herford / Germany
Posts: 986
Some more information I got from various sources:

Reset sequence CSPPC (from NetBSD, OS4):
Code:
P5_REG_LOCK = P5_MAGIC1|P5_MAGIC2;
P5_REG_LOCK = P5_MAGIC1|P5_MAGIC3;
P5_REG_LOCK = P5_MAGIC2|P5_MAGIC3;
P5_REG_SHADOW = P5_SELF_RESET;
P5_REG_RESET = P5_AMIGA_RESET;
The magic sequence unlocks P5_REG_SHADOW. I verified that you can write to it only after that sequence. Any other write access to the P5_MAGICx bits locks P5_REG_SHADOW again.

I'm not sure why this sequence is required and what SELF_RESET is for. Tests show that clearing P5_AMIGA_RESET is sufficient to reset the system.

There seems to be no set/clear bit 7 in P5_REG_LOCK (?).

The other known bit in REG_SHADOW is P5_SHADOW (Bit 0). It may be for mirroring the last 512K of Fast-RAM at 0xfff00000. But after booting in 68k mode the register is 0x4f here, which means SHADOW is inactive? But the mirror at 0xfff00000 is present. So my guess may be wrong.

Edit: Tests show that clearing P5_SHADOW makes the system crash hard. It stays dead even after a normal keyboard reset. You need to press CTRL-Amiga-Amiga 10 seconds to wake it up again. Probably it is a ROM-shadow to copy the ROM somewhere into Fast RAM?

Difference in BPPC reset routine:
Before the unlocking the BPPC needs P5_BPPC_MAGIC = 0.

Code sequence to take over the PPC, after initializing the PPC's reset vector (I used it in my NetBSD bootloader, taken from Linux APUS):
Code:
P5_REG_RESET = P5_PPC_RESET;
P5_REG_INT = P5_ENABLE_IPL;
P5_REG_ENABLE = 0xa8;
P5_REG_ENABLE = 0x10;
P5_IPL_EMU = P5_SET_CLEAR | P5_DISABLE_INT;
P5_REG_RESET = P5_SET_CLEAR | P5_REG_RESET;
The sequence written to P5_REG_ENABLE is a mystery. Looks like:
1. Set bits 3 and 5.
2. Clear bit 4.
Bit 3 would be a PPC to M68k interrupt request? Makes no sense here.

Another interesting fact is that P5_DISABLE_INT seems to be active high, in contrast to most other bits.

Last edited by phx; 05 August 2014 at 21:20. Reason: More details for P5_SHADOW and BPPC reset
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