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Old 05 August 2014, 21:34   #9
Toni Wilen
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 43
Posts: 20,657
Did some real CSPPC tests.

REG_LOCK: Bit 0 is the only one that can be changed. (Write 0x81 -> gets set to 1 and 0x01 -> cleared). Other bits won't change. This register is normally used to unlock flash chip write mode by writing "magic" values in sequence. (0x60, 0x50, 0x30)

IPL_EMU m68k IPL bits seems to be stuck at 7, writing won't change them, reading them in interrupt routine (I used level 3) still returned 7.. Even when ENABLE_IPL was active. DISABLE_INT bit is also stuck at 1. So apparently it is read-only too and perhaps DISABLE_INT and m68k IPL bits only work when PPC is active? (Or maybe even when PPC is interrupt master?)

REG_IRQ: Clearing both bits 3 and 4 (not 2 and 3) are confirmed causing an interrupt. System froze when I cleared both Bits 2 and 5 can be also set or cleared. Bit 6 is stuck at zero.

Speculation mode: PowerUP does something more if I trigger PPC interrupt when bit 0 is active (zero). PPC interrupt code sets it back to one which probably means it really should cause PPC interrupt. But the problem is that it is PPC code that clears this bit, PPC interrupting itself, why? (And after some interrupt it logs unexpected external interrupt crash information to serial port. Nothing appears on screen)

BlizzardPPC flash unlock is totally different. REG_LOCK most likely only has single function, bit 0 + bit 3 is always set as a "I am BPPC" identification bit that for example flash updater checks. Write $42 to $f60092: write-enable flash, write to $f60093: read-only flash. Also maprom works differently, write $f60012: maprom on, write to $f60013: maprom off.
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