View Single Post
Old 04 August 2014, 15:53   #4
phx
Natteravn

phx's Avatar
 
Join Date: Nov 2009
Location: Herford / Germany
Posts: 987
Quote:
Originally Posted by Toni Wilen View Post
F60008 bits 2 and 3 are most likely PPC to M68K interrupt output enable and active bit (just like bits 0 and 1 are enable/active bits for SCSI interrupt), causing m68k int level 2 when both are active.
That's interresting. I hope that some more details will be revealed during this project.


Quote:
But m68k IPL lines are input only (they are physically input only).
Yes, sorry. I wrote nonsense. I just wanted to fix my last posting.

By using P5_PPC_IPL the PPC just emulates the missing M68k SR register. So writing to it masks out lower interrupt levels in the same way as the M68k could do by writing SR.


Quote:
P5_INTLVL: Early boot code uses this register as a 7 bit storage for keyboard keys (esc, s, etc..) which means it has to be normal read/write register and it can't affect m68k side.
Right, you can store 7 bits there, when the M68k is master. But it has a SET_CLEAR bit, like the other registers.
phx is offline  
 
Page generated in 0.05105 seconds with 9 queries