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Old 04 August 2014, 15:06   #3
Toni Wilen
WinUAE developer
 
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 42
Posts: 19,542
Quote:
Originally Posted by phx View Post
As you know, unfortunately nothing is official. This is reverse engineered information, which I have found in AmigaOS4, Linux and NetBSD. I even wrote most of the NetBSD code for the CSPPC-port myself, but it is not working very well...
Yeah, something very important is missing, for example F60020 bit 0 is totally unknown and it has to do something with interrupts.

F60008 bits 2 and 3 are most likely PPC to M68K interrupt output enable and active bit (just like bits 0 and 1 are enable/active bits for SCSI interrupt), causing m68k int level 2 when both are active.

Quote:
A PPC interrupt master will use these lines to directly set the IPLn lines on the mainboard, which the disabled M68k no longer can do.
But m68k IPL lines are input only (they are physically input only). Paula is the only IPL output. There is no way this register is used to set IPL lines as output. Even if it affects only onboard m68k (so it is not conflicting with Paula's IPL outputs), KS interrupt routine would still ignore them as spurious interrupts because Paula INTREQR/INTENAR bits are checked.

Quote:
My guess is that you can use it to enable which individual interrupt levels are allowed to trigger the PPC's external interrupt line
I agree. Early boot code uses this register as a 7 bit storage for keyboard keys (esc, s, etc..) which means it has to be normal read/write register and it can't affect m68k side.
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