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Old 04 August 2014, 14:43   #2
phx
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Join Date: Nov 2009
Location: Herford / Germany
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Quote:
Originally Posted by Toni Wilen View Post
/* IPL_EMU 0x30 */
#define P5_DISABLE_INT 0x40 // if set: all CPU interrupts disabled
#define P5_M68K_IPL2 0x20
#define P5_M68K_IPL1 0x10
#define P5_M68K_IPL0 0x08
#define P5_PPC_IPL2 0x04
#define P5_PPC_IPL1 0x02
#define P5_PPC_IPL0 0x01
#define P5_IPL_MASK 0x07
/* INT_LVL 0x38 */
#define P5_LVL7 0x40
#define P5_LVL6 0x20
#define P5_LVL5 0x10
#define P5_LVL4 0x08
#define P5_LVL3 0x04
#define P5_LVL2 0x02
#define P5_LVL1 0x01

Something to do with interrupts but are they input or output or both?
Both.

As you know, unfortunately nothing is official. This is reverse engineered information, which I have found in AmigaOS4, Linux and NetBSD. I even wrote most of the NetBSD code for the CSPPC-port myself, but it is not working very well...


Quote:
Mainboard inputs?
The P5_cpu_IPLn bits reflect the status of the 68k interrupt mask from the SR register. As you know the PPC has no SR register and no interrupt mask. The 603/604 chips only support a single external interrupt line, which can be masked by the EE bit in MSR, so Phase5 had to find a way to simulate the IPL0..IPL2 lines for the PPC.

On CSPPC/BPPC Amigas there can be only one interrupt master CPU. Either the M68k is interrupted or the PPC. It can be controlled by the P5_INT_MASTER bit (when clearing the bit, the master is PPC). In PowerUp/WarpOS mode the interrupt master is still the M68k, while in a PPC-OS (OS4, NetBSD, Linux) the interrupt master is the PPC.

As I understand, depending on the master-bit, you use either the P5_M68k_IPLn or P5_PPC_IPLn mask. A PPC interrupt master will use these lines to directly set the IPLn lines on the mainboard, which the disabled M68k no longer can do. This means when the PPC receives a serial level 6 interrupt it has to set P5_PPC_IPLn to 6, exactly like a M68k would do.

I can only guess about the M68k-master mode. I think the P5_M68K_IPLn bits only reflects the status of the M68k SR register, in case the PPC needs it.


Quote:
Does writing cause interrupts?
Writing to IPL_EMU? No. See above.

Writing to IPL_LVL...? Hmm. No.
My guess is that you can use it to enable which individual interrupt levels are allowed to trigger the PPC's external interrupt line. In NetBSD I'm enabling all levels on startup. May be only relevant for PPC interrupt master mode.

Last edited by phx; 04 August 2014 at 14:46. Reason: MSR EE, not IE.
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