This board is built for myself at this point, so not everything needs to make sense to you.
If you want to question, go bug fpga arcade as they are probably using external PLL for their clocks too. See their chip labeled as Clock Generator.
>the three on board PLL are used:
>- one for SYSCLK (y0)
>- one for the PLL/NTSC Coder clock (colour burst frequency on y1)
>- one for VIDCLK (y4)
Note: onboard not onchip.
This PCB is not limited for computer emulator. It is also for my
FPGA and ARM eval board. If I want to test out a PLL, where else would I do it?
I don't ask you why you spend that $2 on things, do I?
Oscillator: $1.77 vs Crystal: $0.60 + PLL $1.55
Cost delta = $1.77 - ($0.60+$1.55) = -$0.38 cost saving
for that $0.38, I give you 3 flexible programmable clocks. I think it is a good deal to get a bullet point on marketing.
It is my money and my board. Pay me enough, I would make a board without one just for you. I'll charge a standard consulting rate and in your case no discounts.
You can always design and layout your own board just like I did without any help. I'll make the schematic part open source at some point.
If I need a special odd ball frequency, I can make it. FPGA PLL is very limited vs this.
> Generates up to 8 non-integer-related frequencies from 8 kHz to 160 MHz
(3 in that package)
> Exact frequency synthesis at each output (0 ppm error)
> Glitchless frequency changes
> The device consists of two PLLs—PLLA and PLLB. Each PLL consists of a Feedback Multisynth used to generate
an intermediate VCO frequency in the range of 600 to 900 MHz. Either of these two VCO frequencies can be
divided down by the individual output Multisynth dividers to generate a Multisynth frequency between 500 kHz and
I can ask for 123.456MHz and 2 other odd ball frequencies this chip will give it to me just like that. No approximation nor rounding off. Please show me that the FPGA PLL can do that. Oh yes and on the fly, not precompiled please.