Originally Posted by majsta
Only one thing I didn't understand.
Why do you need external PLL?
It makes a bit easier to recompile other FPGA cores that uses a different clock input without having to play with the PLL setting in the source code. Also at some point if I want to play with pushing clock speeds like overclocking, I can dial in the new clock without recompiling the FPGA core.
Note that is only for part of a design e.g. memory controller as the video might get out of sync.
Amiga PAL (28.375MHz) or NTSC (28.636MHz) mode can now be run at their clock frequency and not just an approximation 28MHz(?). This PLL can generate frequency with resolution a few digits behind the decimal point and not just 1MHz increments like you would find in a PC.
The true story: Originally I was going to use it to generate the 48MHz and FPGA clock from a 25MHz for Ethernet. You pay about the same, but get the flexibility.
Then the layout got crowded. From a signal quality point of view and easy of routing, I have decided to stick individual clocks near the chips. I like the PLL,so it stays. It is a shiny $2 toy I want to play with.