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Old 31 July 2014, 06:21   #18
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Join Date: Jul 2014
Location: Ottawa/Canada
Posts: 49
Originally Posted by robinsonb5 View Post
One question: can the SD card be accessed directly from the FPGA, or does the ┬ÁC "own" it?
I just thought of something. There is a 16-bit data path (multiplexed Address/Data with an address latch signal) from FPGA to the Ethernet & CPLD. The CPLD (XC9572XL) is there to decode address space for both. I place the ATA registers within the Ethernet unused register space and the CPLD translates the bus cycle into the ATA signals. The FPGA is the one that's driving the timing.

So if you are willing to "gut" the ATA, you can deselect the Ethernet chip by latching the ATA address space. At that point, you can simply bit-bang the ATA signals from the FPGA state machine with the data bus (via the CPLD with new bit file). When you are done, let the normal Ethernet bus cycle through. The Ethernet chip has 24kB internal Rx/Tx buffers, so can tolerate a bit of burst SD traffic.

OpenCore has "Wishbone SD Card Controller". Need a software driver for that. 4-bit SD mode should be a decent alternative to ATA for low power applications.

You can hang a SD/MicroSD socket with the full 4-bit SD mode access there with the rest of the I/O for something else. ATA pins are 5V tolerant, but driving 3.3V out with proper series terminations per ATA specs.

If using the ATA pins for SD, the SPI from ARM (already hooked up to the CPLD) can be muxed to "share" the SD while booting. Per SD specs, SD card needs to be power cycled to switch between SPI and SD mode.

There are all kinds of crazy thing you can do within the hardware limitations (under project detail on my URL) as this is a development card and things are programmable/hackable.

Found out today that ARM SPI to CPLD is a no go (before booting FPGA) as it burns too much resources. After the FPGA is loaded, the ARM could talk to both devices via the FPGA.
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