Originally Posted by K.C.Lee
I am going to do ignoring the other 16-bit memory bus until I get the rest of the board going. Even getting a network driver going would have a much higher priority than that. It is a chicken & egg problem to get a 32-bit datapath in the FPGA core developed. So I decided to do that first step.
Actually the 32-bit width should be a fairly easy mod. You might find the projects here: https://github.com/robinsonb5/ZPUDemos
useful for debugging - the SDRAM tester in particular.