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Old 29 July 2014, 09:48   #13
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Join Date: Mar 2012
Location: Norfolk, UK
Posts: 574
Originally Posted by K.C.Lee View Post
I am going to do ignoring the other 16-bit memory bus until I get the rest of the board going. Even getting a network driver going would have a much higher priority than that. It is a chicken & egg problem to get a 32-bit datapath in the FPGA core developed. So I decided to do that first step.
Actually the 32-bit width should be a fairly easy mod. You might find the projects here: useful for debugging - the SDRAM tester in particular.
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