That SDARM is the largest one for that package. SDRAM is going EOL, so don't expect to be any larger one. Not going to use BGA packaging just for 64MB. 16MB for now until I can turn on the x32 databus to get the full 32MB. Given that I had been using 4MB/2MB Amiga in the past, so that's not a big issue for me.
I have only gotten the PCB layout finalized last week and got the board made. Got my confirmation email today that my PCB are going to be arriving in 25 days (give or take). Taking a mental break, that's why I joined this board today.
Then I have to figure how to solder them. Working with 0.5mm pitch, DFN and 0402 parts are not easy. I don't want to spend money on stencils ($20 which is a very good price) nor solder paste ($16), so I am going to try something else to reflow the board.
Haven't done anything with firmware/FPGA cores as this is a one man show. The next step on my list is CPLD and then ARM. I need to get a debug monitor on the ARM and port minimal firmware over to configure the FPGA. I am using a Freescale ARM chip and not the SAM7 chip (for package size, USB OTGa and cost reasons). This is my first time with ARM chip, but I can program 8-bitter and write my bare metal code from datasheet.
My very long term plan is to diverge from the ARM code base. I believe a RTOS is the way to go for my sanity and for things like USB support.
My verilog and VHDL is very rusty at the moment. MiST is the closest parent to the FPGA this new design, so I would start with whatever FPGA cores from that project. I read that he was using Pacman game for debugging MiST, so that would be a big test for memory, VGA etc. I have ordered a Chinese USB Blaster clone, so probably going to use their free logic analyzer (Spinal Tap) for debugging.
Yes, I am doing things as if things are not hard enough. But then again, I have always gotten the high risk and late start projects that one one else want to do.
I am looking forward to reach that stage of the project when 32MB is not enough or having worry about RTG.
I have same amount of FPGA and memory resource as MiST, so my problems will also be MiST's problem.
I have an expansion connector with high speed serial link, so my logical move is to vacate the 68000 core from the FPGA on this board and pop in a daughter card with a shiny FPGA or FPGA with a processor. That should leave enough space for a larger graphic core. My original plan was to use the next sized up $70 FPGA that is in this footprint. It turns out that one has less I/O, so not usable for my design as is.