Originally Posted by FrenchShark
IIRC, the DPLL code I posted handles timings outside 2us/4us cell size as long as the counter is within CTR_MIN_VAL and CTR_MAX_VAL.
GCR (4us bit cell) is handled with the clock enable, I even added HD floppy mode with a faster clock enable. I guess you have added the HD mode on the FPGA Arcade too (maybe even variable bit cell mode) ?
The DPLL logic you have is not correct for bitcell times that exceed the counter min and max, which is often used for copy protection. How Paula handles that is different depending on the number of valid bitcells up to when invalid bitcell is clocked. Paula can handle variable speed bitcells - this is common for Rob Northern protections. GCR is clocked with a different mechanism than MFM bitcells. In my copy and converter programs I turn the DMA on and constantly alter the DMA length register, address register, and sync match register. So, I can have a single DMA transfer that takes a month to complete if I wanted. That is something that no software Amiga emulation handles correctly.