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Old 01 July 2014, 21:45   #139
pandy71
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Join Date: Jun 2010
Location: PL
Posts: 1,546
Quote:
Originally Posted by FrenchShark View Post
This is really no big deal.
I have done it myself. I am sure Mike had no problem implementing that part.
Here is the DPLL verilog code :-)
Read has been tested. Write, not yet.
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Enjoy !!

Frederic
Thanks FrenchShark for nice surprise!!! But side to DPLL there is more things in Paula where there is no information at all (similar for example for Blitter patent where line mode is totally ignored - perhaps due patents violation? Maybe same situation in Paula case - mentioned by Jim GCR functionality - also not covered by HRM)

Quote:
Originally Posted by JimDrew View Post
Yes, Mike is a bit nutty when it comes to direct comparisons to the hardware, shaving chips, x-raying dies, etc.

There are a LOT of details that I discovered about Paula that are well beyond the patent descriptions, and the code above will not emulate Paula fully. You are missing several key elements, and will be missing more when you add the writing support. The DMA integration is one of the biggest problems, and there is of course the GCR module that everyone misses.
Quote:
Originally Posted by JimDrew View Post
You are missing part of the data seperator, specifically for handling timings outside of the normal 2us/4us bitcell size. That code does not handle weakbit or strongbit protections correctly. You need GCR for handling Mac formatted disks, loading some copy protected Amiga disks, and also for analyzing copy protected MFM disks (this is a neat way to scan a MFM disk and see patterns). You must be able to turn on/off/on the DMA randomly, and also change the DMA length counter on the fly without affecting the incoming data. There are a few other little things as well. Paula is far more complicated than most people realize, and it took me a long time to be able to understand how the disk portion really works and come up with the tricks that I did with my copy and converter programs. I learned quite a bit when I changed the speed of Paula via SYBIL.
so any chance to share such details in separate topic for example http://eab.abime.net/showthread.php?t=19676 ?

Also SYBIL sounds curious - i've read about SYBIL few times but in Europe not many people use this HW - do SYBIL is reprogrammable (controlled by software) clock source connected to video port (and by this able to change system speed in variable way)?

Thanks in advance!

Quote:
Originally Posted by turrican3 View Post
could it be possible technically to include aga to make amiga 500 compatible aga, and what's the limits of this approach ???
AFAIR Commodore mentioned such possibility in Budgie description - Budgie should be able perform conversion between 16 bit CPU bus and 32 bit CHIP AGA bus.
So this should be possible - A3000 schematics have something like Budgie but on TTL - bunch of 74646 buffers mostly.

Quote:
Originally Posted by FrenchShark View Post
The difficulty with AGA on A500/A2000 are the 8520s that must run at 1.4 MHz. You need at least a small FPGA card to replace the original 8520s (maybe there are 2MHz 8520s in DIL package somewhere ?).

Regards,

Frederic
Are You sure? E clock is same for A1000 and for A4000 - seem that 8520 are the same speed...

Last edited by pandy71; 01 July 2014 at 22:12.
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