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Old 10 June 2014, 16:10   #4
Toni Wilen
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 43
Posts: 20,657
Originally Posted by ovale View Post
In another thread you said that the CPU is free to use even or odd cycles.
I inferred that it could used both.
CPU memory cycle can _start_ during odd or even dma slot but 68000 memory access cycle is still 4 cycles and it always takes (at least) 2 dma slots.

Normally bus would be completely allocated for the CPU during memory access cycle but Amiga uses trick that allows it to interleave CPU and DMA cycles.

When CPU does addressing part of memory cycle (~first half of memory cycle, simplified), Agnus "only" stores the CPU address but it can also simultaneously do DMA transfer to/from chipram because data bus is still free (there are data latch chips between CPU and Agnus that insulates CPU side and chipset side of bus). Only second DMA slot is "used" for CPU data transfer. And if second slot is required for DMA, Gary tells CPU that memory is not ready ("simulated" memory wait state), please wait..

From CPU point of view memory access looked normal (possibly very long in worst case..) 68000 memory access where the CPU was in control of the access cycle, from Agnus point of view CPU was tricked

AFAIK all Amigas have same design, only way to have fast CPU memory accesses is to have local fast ram. A3000 and AGA implemented 32-bit wide CPU chip memory access.
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