View Single Post
Old 22 July 2013, 13:48   #513
majsta's Avatar
Join Date: Jun 2010
Location: Banjaluka/Republic of Srpska
Age: 37
Posts: 431
What I can conclude from the picture:
1. No more trapdoor connection socket?
2. I don't see how IDE can autoboot without using another address space and new driver becauuse don't see anywhere OVR, INT2 connections.
3. See problems with RTC and battery, because voltage for RTC are used from voltage regulator not from battery?
4. Any additional riser slot can cause disturbance to 7MHz clock so edges can't be captured properly.
5. Don't understand purpose of top right connector (logic analyzer maybe if so why didn't use JTAG).
6. Purpose of Spartan generating few things:
a) Rising and falling edges of 7MHz clock
b) SDRAM controller
c) Driving DIR and OE signals to buffers
d) RTC timings
e) IDE controller and possible part of Gayle logic

From my point of view design looks perfect I can't see anything done wrong but if I may say it could be tricky to get proper timings related to CPU and faster SDRAM so maybe there are some caches. What could be one of the problems also. On A500 motherboard are 2 large electrolytic capacitors who can give some problems when you want to attach board like this. You solved one like I can see but another one is under this board so you had to add new riser slot or change capacitor on A500 board.
majsta is offline  
Page generated in 0.03980 seconds with 10 queries