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Kalms · 21 July 2013, 22:14

You are on the right track. There are a couple of things which you need to consider though.

The blitter is reading and writing words. These memory accesses have to be to even word addresses. You can't make the blitter write misaligned words.
If you want the blitter to write a smaller unit than a word, then you need to read from the output area and include that into the blit operation as another masking step. You are out of blitter channels in your case so you can't do that in any sensible way.

Blitter performance when you have two active source and one active destination DMA channel is about 40kB/frame on a stock A1200. If you run ordinary CPU code at the same time then it shares chipmem bandwidth with the blitter - so both the CPU code and the blit operation will run correspondingly slower.

When you do a merge operation such as the one you described above then you need to be able to shift sometimes to the left, and sometimes to the right. You shift to the left by performing a descending blit. In your example you would do blit #1 and #3 ascending, and blit #2 & #4 descending.

Given the above (particularly the 'blitter always reads and writes words') your current dataformat will require you to do two blitter passes; one with 4-bit shift length and another with 8-bit shift length.

You can get rid of the 8-bit blitter pass by doing it in the CPU or by using MOVEP writes (this works on all machines except 68060, and do consider, MOVEP.W to chipmem will do twice the number of write accesses than a normal MOVE.W) or by having longword-pixel-sized prescrambled textures. Or perhaps in other ways.

21 July 2013, 22:14	#3
Kalms Registered User Join Date: Nov 2006 Location: Stockholm, Sweden Posts: 237	You are on the right track. There are a couple of things which you need to consider though. The blitter is reading and writing words. These memory accesses have to be to even word addresses. You can't make the blitter write misaligned words. If you want the blitter to write a smaller unit than a word, then you need to read from the output area and include that into the blit operation as another masking step. You are out of blitter channels in your case so you can't do that in any sensible way. Blitter performance when you have two active source and one active destination DMA channel is about 40kB/frame on a stock A1200. If you run ordinary CPU code at the same time then it shares chipmem bandwidth with the blitter - so both the CPU code and the blit operation will run correspondingly slower. When you do a merge operation such as the one you described above then you need to be able to shift sometimes to the left, and sometimes to the right. You shift to the left by performing a descending blit. In your example you would do blit #1 and #3 ascending, and blit #2 & #4 descending. Given the above (particularly the 'blitter always reads and writes words') your current dataformat will require you to do two blitter passes; one with 4-bit shift length and another with 8-bit shift length. You can get rid of the 8-bit blitter pass by doing it in the CPU or by using MOVEP writes (this works on all machines except 68060, and do consider, MOVEP.W to chipmem will do twice the number of write accesses than a normal MOVE.W) or by having longword-pixel-sized prescrambled textures. Or perhaps in other ways.