Quote:
Originally Posted by keropi
the 49.500 pixel clock is missing from the list so I can't create a 75hz screen... clocks jump from ~42 to ~62 without any middle values.

Here's a clear statement  thanks for that. I'll introduce more pixelclocks in that gap with the next release. The PLL won't exactly reach the 49.5MHz, but on a PAL machine, you'll have 49.657MHz. I also noticed that the exact double of the Amiga pixel clock is missing from the list, so I'll add that as well. This will enable you to "manually" create a VSynced output screen. The exact triple is already there (core A06).
@everyone: If there's an output pixel clock that you require to approach your desired output screenmode, just let me know, and I'll see if that's possible. You can calculate the possible pixel clocks with:
where:
f is the resulting pixelclock in MHz
28.37516 may be replaced by 28.63636 in case of an NTSC machine
m is a wholenumber multiplier between 1 and 32 (both including)
C is a wholenumber divider between 1 and 18 (both including)
m and C make the filename extension of a core: C is an index to the alphabet, so you get a character between A and R. The the 2digit number after that is the mvalue.
The output pixel clock for 640x480 is very low at around 25MHz. I may have to recalculate the PLL filter values in order to get that stable (i.e. get rid of temperaturedependency). The filter values are currently calculated for higher pixel clocks ranging from 40 to 135 MHz.
Jens