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Old 13 March 2013, 19:03   #434
strim
NetBSD developer
 
Join Date: May 2012
Location: Warsaw, Poland
Posts: 398
Quote:
Originally Posted by mr.vince View Post
The source for the FPGA will allow you to add more features and tinker with it. If you're a power user and you "break" it, connect the JTAG and revive it.
That's sweet as hell. I've recently started learning VHDL and already have some insane ideas to prototype. Now I have Nexys3 interfaced to clockport, but having access to signals present on CPU socket will be much more fun.
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