Originally Posted by mr.vince
The source for the FPGA will allow you to add more features and tinker with it. If you're a power user and you "break" it, connect the JTAG and revive it.
That's sweet as hell. I've recently started learning VHDL and already have some insane ideas to prototype. Now I have Nexys3 interfaced to clockport, but having access to signals present on CPU socket will be much more fun.