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Old 26 December 2012, 02:58   #29
Leandro Jardim
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Join Date: Nov 2009
Location: Legoland
Age: 37
Posts: 1,129
Originally Posted by spud View Post
The 512x192 mode (mode 3) is only 2 bits per pixel. It needs just a 24KB frame buffer you can place anywhere you like in available RAM, taking up one and half pages. All the memory, including whatever you assign to the frame buffer can be paged in and out at will, you only need the frame buffer paged in to update it, once done, page it out and you have use the memory space for something else.

SAM doesn't use I/O registers for writing to video ram. It is all part of that 64KB memory block addressable to the Z80.
Thanks, was good that you explained!

When I read the SAM specs, shortly after I posted the first message, I tought that it used two bank switch schemes, one for the CPU and other for ASIC, for example, for the CPU a multiple of 16kb, and for the ASIC multiples of 24 kb. The ASIC could use a mirrored view of the memory map of the CPU where only the page multiple is different. As such would there is no way to switch slots in the ASIC, but the position of the memory of the two schemes could be thus "interlaced" with each other.

I did this assumption because acessing the bottom of the framebuffer with pages of 16 kb should be very difficult. For example, copying a bitmap from the top to the bottom of the framebuffer, if you can access only one half of it at once...

It should be very hard for you programmers of the SAM!

Last edited by Leandro Jardim; 26 December 2012 at 21:19.
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