View Single Post
Old 22 December 2012, 19:09   #3
Registered User
Join Date: Aug 2004
Posts: 2,828
It wouldn't make vblank-synced programs run at half speed, since the vertical blank interrupt is generated by the custom chips independent of the fact that the HSYNC and VSYNC pins on Agnus are used as reset inputs when a genlock is connected. But there could be issues with programs which use the CIA TOD counters. For example a program which times disk head stepping using CIA-B TOD would step at half-speed when the genlock has an active video signal input. [Since the HSYNC signal is at half line rate, see below.]

The Amiga 1000 and 2000 (probably 3000 and 4000 too?) use the power supply tick for the CIA-A timer. So the genlock doesn't affect CIA-A TOD on those machines, it's just with the A500 that something strange could happen. The A/B2000 can be jumpered to use vsync as CIA-A tick, but it wasn't shipped like that from the factory.

Basic summary:
  • With interlaced source video input to the genlock, the VSYNC line gets pulsed on each odd field, i.e. at ~30Hz for NTSC. On the A500 the VSYNC line is connected to CIA-A TICK.
  • With non-interlaced source video input, the VSYNC line is pulsed on every field, i.e. at ~60Hz for NTSC.
  • With both interlaced and non-interlaced source video input, the HSYNC line is pulsed every two scanlines. The HSYNC line is connected to CIA-B TICK.
  • With no video input signal the Amiga generates its own syncs.
When the genlock is connected, the genlock generates horizontal and vertical reset signals which it derives from the incoming source video signal. (With no video signal present the genlock provides the Amiga master clock signal but the Amiga generates its own sync signals.) The Agnus HSYNC and VSYNC pins are inputs when the genlock is connected with incoming video signal.

Looking at the A500 schematic, the Agnus VSYNC line connects to pin 12 of the 23-pin video connector and CIA-A pin 19 (TICK). Similarly Agnus HSYNC connects to video connector pin 11 and CIA-B pin 19.

The HSYNC connection to CIA-B pin 19 is basically the same with the A2000 and B2000. So probably all Amigas can have a half-frequency HSYNC signal applied to CIA-B with genlock & active input video signal.

I read the A1300 genlock service manual (P/N 314983-01). [Anyone know if a scanned version is available online?]

If no video signal is present the Amiga generates its own sync signals. So no problem there. The difference comes when there is a video signal present. Then the genlock drives the Agnus HSYNC and VSYNC pins. And consequently the CIA-B tick pin. And for A500 or suitably-jumpered A2000, the CIA-A tick pin too.

For normal interlaced input video the VSYNC input is pulsed on every odd field, i.e. at ~30Hz for NTSC. With non-interlaced input video (e.g. perhaps from some VCRs or another Amiga) the VSYNC input is pulsed every field/frame, i.e. at ~60Hz for NTSC.

About the horizontal reset signal (HSYNC):
The horizontal reset circuit consists of U17B and U14B. The reset signal occurs on the alternate cycle of the horizontal beam counter. The FF U17B is toggled by the rising edge of RGH, and U14B is triggered by the rising edge of the U17B output. A 32 usec reset pulse is sent to the computer at the beginning of every other line.
About the vertical reset pulse (I've deleted parts for brevity):
The vertical reset pulse is generated on the even odd fields to reset the vertical beam counter of the computer. ... one can determine whether the start of the vertical synch is coincident with the beginning of a line or shifted by half a line. The circuit is configured to detect even odd fields, and is connected to the vertical reset logic so that the reset to the computer is sent on the even odd field. The vertical reset circuit ... generates a 64 usec pulse immediately after the detected vertical synch. ... NAND gate gates the reset pulse during the even field.
There are probably misprints in the text, where I think it should say odd instead of even. The vertical timing diagram indicates that the V/2 reset pulse happens on odd fields, and says "With non-interlaced video source input the V/2 RESET will occur on every field. This applies to both odd-field only and even-field only video sources."

Originally Posted by Toni Wilen View Post
Perhaps some models (Commodore only?) had this "feature"? I have used some 3rd party genlocks and I don't remember anything weird happening.
If you still have access to a genlock, hook it up to an Amiga and apply an interlaced video signal to its input (e.g. from a DVD player or whatever). Then you should be able to write a test program to check the CIA TOD clock rates.

Last edited by mark_k; 22 December 2012 at 19:30.
mark_k is offline  
Page generated in 0.14526 seconds with 9 queries