Originally Posted by mr.vince
Herzi has done the impossible and even enhanced chip mem write speed which is troublesome, because chip mem is in your Amiga and not on the Zeus board.
Careful with these "enhancements" - not all Agnus types like a late start of the access. I've tried that as well, but found that it's better to make it a user-option rather than a standard setting. Especially the NTSC 8370 Agnus (the "first ever" fat Agnus) is piccy. Also, an early end of the access will most probably only work on newer boards with faster memory chips. I've had the exact same idea when working on a Rev.8 A500 board, but quickly found that it's best to continue testing with a Rev.5 board that has 150ns RAMs (worst-case). The combination of "late start" and "early end" for read access will only work on later boards, and "early end" for writes doesn't work at all, as you probably violate data-hold times.
Commodore has used all kinds of memory chips in the A500 (always the cheapest on the market!), so going fancy on chipmem access bears quite some dangers. You won't be able to increase the average of 3.5MBytes/s to chipmem, but you may gain a cycle or two of execution between chip(ram/register) accesses.
You should use Bustest instead of AIBB - it's way more accurate and will show a higher number. That's way better for your promotion ;-) I believe that the actual performance of your Fastram is way higher then 7MB/s. You should get something close to 25MBytes/second for 0-waitstate or 16.6MBytes/second for 1-waitstate.