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Old 13 October 2012, 15:51   #254
Join Date: Jun 2010
Location: out in the wild
Posts: 1,245
that won't work. Simulation of the logic shows a max. frequency of 50.7MHz. The CPLD is really full with all those memory-tricks and the freezer logic. I had to route some things through several macrocells, and I had to use extender product terms of the chip, which also make things slower. However, it's running perfect in real-life at the frequency it is supplied with.

Changing the CLK divider is possible, but won't be publicly documented. It's a 16MHz CPU and the databook clearly says that 16,67MHz is the maximum allowed frequency. If you decide to hack the card, I'm officially out of the game. If I make a public documentation, this might be mistaken for a "recommended way to do it", but the only recommendation I can give is to leave it as supplied. It's quite fast for a 16MHz card.

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