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Old 17 August 2012, 21:36   #149
Join Date: Jun 2010
Location: out in the wild
Posts: 1,245
Originally Posted by SpeedGeek View Post
Yes, but AS is asserted 1/2 clock after the cycle begins unless a cache hit causes the 68030 to abort the external cycle! So it's 1.5 clocks from AS or 2 clocks from ECS.
Here's a quick hack: Disabled one of the two 64M banks and added a simple equation that pulls STERM as soon as AS becomes valid on the area. CPU is a 68030RP25C, clocked at 25MHz. This looks like a single cycle to me:
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However, you also see a problem with ECS and cache active: If the CPU hits a valid cache entry, the time until the next ECS is very short. Now if you open a row "just in case", you must go through the whole cycle of precharge and Precharge-to-row-open time before you can open the next row. Trouble is that the CPU may start the next access no more than two cycles after that, and you must be ready, otherwise you don't win but even lose time.

Disabling the cache makes sure that there's always an access after ECS:
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At true 0-waitstate, I wanted to know the difference between "cache and no cache", so I tried bustest. First with all caches disabled:
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...and then with all caches on (which also turns caches&burst on for the Bustest inner loop):
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...and this looks like a measurement error to me, 'cause the read values are too close together. Write value is even more of an indication of a measurement error, because Cache is not updated on writes. Only the fastmem, which gains a lot from bursts, is a tiny bit faster.

Originally Posted by SpeedGeek View Post
With your 2x clocked SDRAM I would be surprised if you didn't beat the crap out of any older DRAM based design operating at similar (68030) clock speeds.
I may be a memory cycle short to complete the time after precharge, but this quick measurement hack shows me that my idea of "external cache equals internal cache performance" is close to being correct. You must be right in terms of "burst helps", because fastmem with cache+burst is faster than the 0-waitstate area.

I'll need triple memory speed vs. CPU speed to really become fast enough to "play cache". Is it worth it? Not sure. I have to sacrifice at least one pin on the logic chip, and pins is what I'm always short of. I'd have to work on the memory controller in terms of "close the row ASAP if no access" in order to work with cache, and I need more state-bits for the memory controller because I need to stretch burst accesses. Need to draw some state diagrams...

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