View Single Post
Old 17 August 2012, 18:32   #148
Registered User
SpeedGeek's Avatar
Join Date: Dec 2010
Location: Wisconsin USA
Age: 54
Posts: 378
Originally Posted by Schoenfeld View Post
Really? The way I'm reading the datasheet is that STERM is sampled on the next half-clock after AS, and the cycle can be completed on the half-cycle after that, so the total time after AS would be a single cycle.

If you count from ECS, this would be 1.5 cycles. Either way, it's a full cycle less than the fastest access that I have done before. ACA1231 beats the crap out of the B1230-IV, despite almost 20% lower clock rate. So much for "on-chip cache hit rate of the 68030".

Yes, but AS is asserted 1/2 clock after the cycle begins unless a cache hit causes the 68030 to abort the external cycle! So it's 1.5 clocks from AS or 2 clocks from ECS. With your 2x clocked SDRAM I would be surprised if you didn't beat the crap out of any older DRAM based design operating at similar (68030) clock speeds.
SpeedGeek is offline  
Page generated in 0.04001 seconds with 10 queries