Originally Posted by Schoenfeld
Well, the 68030 is more than that, especially with it's faster bus interface.
Disabling the cache would be well within specifications. There is a pin on the CPU that is dedicated to doing just that. It has nothing to do with "defective". Motorola has prepared the 68030 bus interface for an external cache controller, and if I can make a memory controller that is as fast as a cache-hit, you don't require the on-chip caches any more. It would be like 128MByte first-level-cache (well, if it works the way I'm thinking).
The 68030 can run a 2 clock synchronous (external) cycle. However, the internal cache can be accessed in one clock. So an external cache will never be as fast as internal but you can get pretty close with a 2+1+1+1 burst cycle on reads. If can you can make a memory controller which can do that for fast memory than the external cache would be obsolete.