Originally Posted by Schoenfeld
Well, the 68030 is more than that, especially with it's faster bus interface.
Disabling the cache would be well within specifications. There is a pin on the CPU that is dedicated to doing just that. It has nothing to do with "defective". Motorola has prepared the 68030 bus interface for an external cache controller, and if I can make a memory controller that is as fast as a cache-hit, you don't require the on-chip caches any more. It would be like 128MByte first-level-cache (well, if it works the way I'm thinking).
Sure, "defective" is not the good word. I would like to said that using an external cache you may clock the 68030 faster, if the internal cache was a limitation to increase the speed.