You're assuming that memory speed is a bottleneck. It isn't. The 68020 will run 0-waitstate with 1/2 or 1/3 divider. Even at 66MHz mem and 33MHz CPU clock. Who said a 68020 can't be fun :-)?
For the 68030, triple mem speed compared to CPU clock doesn't help, as it only gains half a clock cycle. In order to gain speed at all, you need to gain a full cycle in order to shave off a waitstate. You might think that this may work for a divider of 4 and 100MHz memory speed, but it's not that easy either, because if you go higher with memory speed, you must insert NOP cycles in order to meet memory timing requirements.
The one thing I always wanted to try is to disable 68030 caches completely and start cycles early with the ECS signal (external cycle strobe). I might prepare the mass-production boards for that - maybe I'll have time for that someday :-)