View Single Post
Old 16 February 2012, 21:50   #2319
Registered User
SpeedGeek's Avatar
Join Date: Dec 2010
Location: Wisconsin USA
Age: 53
Posts: 306
Originally Posted by Schoenfeld View Post
I have even contemplated making a fastmem expansion for the 2630, because it's fairly easy-going at 25MHz. However, I fear that capacitive load on the data bus plus the resistor packs (pull-downs) will put enough load on the LXC16245 drivers that timing specs can't be achieved. For a 2-1-1-1 burst, you may have to remove all onboard memory chips (they hang off the data bus without drivers).

Of course you can work with an even higher clock (not x2 but x3) and make data valid a good 5ns earlier, but that goes into the same direction as hacking the card to over 50MHz ;-)

For some real speed gain, I'd pull the EXTERN signal for pretty much every bit of memory that the 2630 can address - including 00c0.0000, the Z2 memory area and (optionally) kickstart. Drawback: DMA would not work any more. Advantage: The whole system would be a lot faster, because any slower memory (except chipmem) would be switched off.

The A2630 has many design bugs (it just barely works @ 25 MHz) including the 1K pull-downs which are sometimes installed as pull-ups! You will spend 20x the time fixing the bugs that you spend replacing the oscillator and 68030/68882 chips.

The memory expansion connector is unbuffered and could not possibly support a 1 TTL load on the address bus even though the specs say so.

I would probably pull the A2630 on board DRAM before I would consider any memory expansion board SDRAM. There are many more problems and bugs which can't be solved by EXTERN. (insert 5 more pages here). I managed to get an AIBB latency of 7.2 with the on board DRAM @ 52 MHz and that's pushing the address decoding, cycle start and bus arbitration logic to its very limits. If the +5 Volt supply is low this fails.

I managed 8 + 2 + 2 + 2 clock cycles with burst @ 52 MHz on the DKB2632 and I may be able to get 6 + 2 + 2 + 2 with faster address buffers. I would not try to run SDRAM @ 2x this clock. If I could get 4 + 1 (or 2) etc. and eliminate expansion board memory I would be happy with that.

Last edited by SpeedGeek; 16 February 2012 at 22:49.
SpeedGeek is offline  
Page generated in 0.05315 seconds with 9 queries