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Old 23 December 2011, 21:13   #1
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Join Date: Dec 2007
Location: Bath, UK
Posts: 119
Hardware Idea: Making use of microcode to improve 68k emulation performance

Hi all,

I've just found out a little bit about how CPU microcode works, and had what could possibly be a braindead idea to use it to improve 68k emulation performance. I should make it clear I'm fully aware I'm out of my depth here, so what I'm about to say could be complete baloney.

Idea came after reading this ReactOS newsletter:

Quoted text in particular:
Most programmers understand that processors conform to an Instruction Set Architecture, specifying what instructions and operations the processor can execute. What many people are unaware of or do not think much about is the fact that most processors do not directly execute instructions as specified by the ISA. Instead, there is a lower level of commands known as microcodes that control the operation of the processor to produce output conforming the an ISA. These microcodes are for the most part completely undocumented as AMD and Intel treat them as trade secrets. Modern CPU designs however are extremely complex and hardware bugs can slip in which do not correctly obey a microcode. Fixing such an issue in hardware would require changing the design, but modern CPUs can actually be patched with updated microcode to compensate for these errors.
So what I'm getting from this is that the functions in the x86 ISA are not written directly to the silicon, but instead implemented in microcode, which allows for flexibility in routing around hardware bugs, and optimising performance. This also ties in with things I've heard about modern x86 CPUs, that at their core the architecture is more RISC-like, and the CISC x86 design is built on top of this.

My main question is this: To what level could you make a modern 'x86' CPU behave like a 68k CPU through use of microcode? For example, if you had a multicore machine, could you make one of those cores execute instructions from the 68k ISA without requiring use of the x86 ISA for translation?

If implementing the 68k ISA in microcode on an x86 CPU wasn't possible, could microcode be used to optimise 68k emulation so that 68k instruction execution took fewer CPU cycles?

Your thoughts please. Thank you.

P.S. If anyone has any good introductory articles about microcode they could link to, please share them so I/we can learn more. Thanks.
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