Quote:
Originally Posted by SpeedGeek
@pandy71
My A2000 w/A2630 already works that way! The 68030 masters the bus and the motherboard continues to get the E clock from the 7 Mhz 68000. Why is this so difficult to understand?
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Please check A2620 PAL equations for U308 and U309.
Quote:
Originally Posted by Kai
Look a the design of the LUCAS accelerator - they still manage to provide the all important E clock at the right speed - despite having the 68020 and 68881 clocked at 16Mhz
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Please check PAL U4 equations.
Quote:
Originally Posted by Zetr0
@Pandy
A two layer board reasonably designed should see 28 / 33Mhz frequency operation.
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I saw plenty 2 layers PCB's that works even on 13GHz but usually as antennas
and this is my point - accelerator without RAM (fast, 32 bit access) have no sense at all - imagine using for example some DDR/DDR2/DDR3 RAM chip even as a RAD-like device
Quote:
Originally Posted by SpeedGeek
@Zetr0
from my October, 1985 Motorola 68000 manual:
"E is a free-running clock and runs regardless of the state of the bus on the MPU."
The A2630 logic does not keep the motherboard 68000 in reset. In fact since reset is common to all the custom chips it's essentially a full motherboard reset! The A2630 simply asserts BR to the 68000 and waits for the 68000 BG. When BG is acknowledged the A2630 asserts BGACK and masters the bus until the next reset or some other Zorro2 device requests the bus.
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Why Commodore implement Gayle as E source? all CIA'a timing on A600 is performed by Gayle - from CPU point of view this is fully asynchronous design with DTACK.