Dug this out of the internet (took a few days). It's originally designed for an Atari ST, although, i can't see why it'd be much different for the Amiga, or even a 68k based Macintosh.
Here's the schematic:
Here's the parts list:
Code:
Semiconductors:
IC1: MC68000-16
CPU 16MHz
IC2,IC3: IDT7174S-35 or CY7C185-15PC (15ns CMOS Parts)
CACHE RAM 8K x 8bit 35ns
IC4,IC5: 6264-LP10 or CY7C185-20PXC (20ns CMOS Parts)
CMOS-RAM 8K x 8bit 100ns
IC6: GAL20V8-25
IC7,IC8: GAL16V8-25
IC9: 74AS00 4-NAND
Resistors:
R1-R4: 4.7 KOhm
R5: 200 Ohm
Capacitors:
C1-C9: 100nF Ceramic
Misc:
64-pin DIP Socket
2 x 32pin SIP Headers
Here's the GAL Equations:
IC6
Code:
Cache controller for MC68000
Address Decoding
*IDENTIFICATION
CCDT1V1C;
*TYPE
GAL20V8;
*PINS
A23 = 1,
A22 = 2,
A21 = 3,
A20 = 4,
A19 = 5,
A18 = 6,
A17 = 7,
A15 = 8,
A13 = 9,
A11 = 10,
A9 = 11,
A7 = 13,
A8 = 14,
A12.T = 16,
A14.T = 17,
A16.T = 18,
A6.T = 19,
MEM.T = 20, % RAM/ROM-Access %
A10.T = 21,
/FCS.T = 22, % FPU Chip Select %
A5 = 23;
*BOOLEAN-EQUATIONS
A6.E = GND ;
A10.E = GND ;
A12.E = GND ;
A14.E = GND ;
A16.E = GND ;
MEM = /A23 & /A22
+ A23 & A22 & A21 & A20 & A19 & A18 & /A16
+ A23 & A22 & A21 & A20 & A19 & A18 & /A17;
FCS = A23 & A22 & A21 & A20 & A19 & A18 & A16
& A15 & A14 & A13 & A12 & A11 & /A10 & A9 & /A8 & /A7 & A6 & /A5;
*END
IC7
Code:
Cache controller for MC68000
Cache & Bus Control
*identification
CCDT2V6;
*type
GAL16V8;
*pins
/PAS = 1, % Delayed AS-Signal %
/UDS = 2, % Upper Data Strobe (Processor) %
/LDS = 3, % Lower Data Strobe (Processor) %
/WR = 4, % Read/Write %
/AS = 5, % Address strobe (Processor) %
CEN = 6, % Cache On-Off %
MEM = 7, % RAM/ROM-Zugriff %
/BGACK = 8, % Bus Grant ACKnowledge %
HIT = 9, % Cache-Result %
EN_I = 11, % Cache Enable (Feedback) %
ENAB.T = 12; % Cache Enable (Output) %
/CWE.T = 13; % Write Enable Cache-RAMs %
/LDWE.T = 14; % Write Enable lower Data RAM%
/UDWE.T = 15; % Write Enable upper Data RAM %
/BLDS.T = 16, % Lower Data Strobe (bus) %
/BUDS.T = 17, % Upper Data Strobe (bus) %
/BAS.T = 18, % Address Strobe (bus) %
/DOE.T = 19, % Output Enable Data-RAMs %
*boolean-equations
BAS.E = /BGACK;
BAS = AS & PAS & /EN_I
+ AS & PAS & /MEM
+ AS & PAS & WR
+ AS & PAS & /HIT
+ AS & BAS;
BLDS.E = /BGACK;
BLDS = PAS & LDS & /EN_I
+ PAS & LDS & /MEM
+ PAS & LDS & WR
+ PAS & LDS & MEM & /WR & /HIT
+ PAS & UDS & MEM & /WR & /HIT
+ LDS & BLDS
+ UDS & BLDS;
BUDS.E = /BGACK;
BUDS = PAS & UDS & /EN_I
+ PAS & UDS & /MEM
+ PAS & UDS & WR
+ PAS & UDS & MEM & /WR & /HIT
+ PAS & LDS & MEM & /WR & /HIT
+ UDS & BUDS
+ LDS & BUDS;
CWE = EN_I & BAS & ( UDS + LDS ) & MEM & /WR & /HIT
+ ( UDS + LDS ) & CWE;
DOE = ( UDS + LDS ) & MEM & /WR & HIT & /CWE & EN_I;
UDWE = EN_I & PAS & ( UDS + LDS ) & MEM & ( /WR & /HIT + WR & UDS & HIT )
+ ( UDS + LDS ) & UDWE ;
LDWE = EN_I & PAS & ( UDS + LDS ) & MEM & ( /WR & /HIT + WR & LDS & HIT )
+ ( UDS + LDS ) & LDWE ;
ENAB = /AS & CEN + AS & EN_I + CEN & EN_I ;
*END
IC8
Code:
Cache controller for MC68000
DTACK control & Cache Refresh
*identification
CCDT3V8;
*type
GAL16V8;
*pins
CL8 = 2, % 8 Mhz Clock %
/SDT = 3, % System DTack %
/FCS = 4, % FPU Chip Select %
/RESET = 5, % Reset %
/BGACK = 6, % Bus Grant ACKnowledge %
MEM = 7, % RAM/ROM-Access %
/WR = 8, % Read/Write %
HIT = 9, % Cache-Result %
ST0.R = 12, % Bit 0 State Encoding %
/PDT.T = 13, % Processor DTACK %
ST1.R = 14, % Bit 1 State Encoding %
ST2.R = 15, % Bit 2 State Encoding %
/PAS.R = 16, % Delayed AS-Signal %
/CLR.T = 17, % Cache-Refresh %
/AS.T = 18, % Address strobe (Input) %
ENAB.T = 19; % Cache Enable (Input) %
*boolean-equations
ENAB.E = GND ;
AS.E = GND ;
CLR = BGACK + RESET + /ENAB ;
PDT = ST2 & /ST1 & /ST0 & PAS % Condition S5 %
+ ST2 & /ST1 & ST0 & PAS % Condition S6 %
+ ST2 & ST1 & ST0 & PAS % Condition S8 %
+ FCS & AS & SDT; % FPU-Access %
ST0 = AS & /RESET & /FCS & /PAS
+ AS & /RESET & ST1 & /ST0
+ AS & /SDT & /RESET & /ST2 & ST1
+ AS & /CL8 & /RESET & /ST2 & ST1
+ /RESET & ST2 & /ST0
+ AS & /WR & /RESET & ST2 & ST1;
ST1 = AS & MEM & HIT & /WR & ENAB & /RESET & /FCS & /PAS
+ AS & /RESET & /FCS & /ST2 & /ST1 & ST0
+ AS & /RESET & ST1 & /ST0
+ AS & /SDT & /RESET & /ST2 & ST1
+ AS & /CL8 & /RESET & /ST2 & ST1
+ AS & /WR & /RESET & ST2 & ST1;
ST2 = AS & MEM & HIT & /WR & ENAB & /RESET & /FCS & /PAS
+ AS & SDT & CL8 & /RESET & /ST2 & ST1 & ST0
+ /RESET & ST2 & /ST0
+ AS & /WR & /RESET & ST2 & ST1;
/PAS = RESET
+ ST2 & /ST1 & ST0
+ WR & ST2 & ST1
+ /AS & ST0
+ /FCS & /ST2 & /ST1 & /ST0 & PAS
+ /AS & /ST2;
*END
So what do you guys reckon? Anyone feel like knocking up a PCB or a Gerber?
