Originally Posted by BuZz
pata seems like a strange choice over sata. I wonder why that was.
At a guess I'd say it was the FPGA/CPLD they chose. To emulate SATA you'd need one with built in high speed SERDES capable pins (RocketIO for Xilinx) whereas PATA could be done with regular pins.
Plus PATA is effectively CF, a medium widely used with Amiga's.
Have they actually released anything to go into the FPGA to developers?