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Old 07 January 2011, 18:31   #1453
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This was Jens post:

Originally Posted by Schoenfeld View Post
The divider is in the CPLD, where all the async mainboard interface and the SD-Ram interface is located. Also, it is critical that the SD-Ram controller and the CPU run in sync - a simple clock-doubling for the CPU would not work at all. As I mentioned earlier for the ACA1230, the two cards (28MHz and 56MHz) look the same, but the CPLD contents are substantially different. It's a whole new development.

I really can't help anyone who wants to do weird things to his accelerator. I shouldn't even start to get into this much detail. If you haven't developed an accelerator yourself, you can't do it. I'm not just saying this to protect myself from too much customer support work. I am doing this to protect you from a failure waiting to happen, unless you have at least the same knowledge as Oliver and I have.

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