Originally Posted by Schoenfeld
The divider is in the CPLD, where all the async mainboard interface and the SD-Ram interface is located. Also, it is critical that the SD-Ram controller and the CPU run in sync - a simple clock-doubling for the CPU would not work at all. As I mentioned earlier for the ACA1230, the two cards (28MHz and 56MHz) look the same, but the CPLD contents are substantially different. It's a whole new development.
I really can't help anyone who wants to do weird things to his accelerator. I shouldn't even start to get into this much detail. If you haven't developed an accelerator yourself, you can't do it. I'm not just saying this to protect myself from too much customer support work. I am doing this to protect you from a failure waiting to happen, unless you have at least the same knowledge as Oliver and I have.
Sorry Jens, I just asked it to clarify if it was a possibility, as I am pretty sure I'm not the only one with the idea and some would be hackerz would have a go at it and possibly damage their boards if it was not clear. Now that you've made it exactly clear, we have information from the most reliable source to refer when the same question comes about in the future (I am pretty sure it will).
anyway, I am looking forward to laying my hands (and only hands, no soldering iron hehe) on your ACA630 (and possibly a ACA1230 if I can) and wish you best of luck with your future projects