Just gained another 1.5% speed!
As I mentioned earlier in this already-fairly-long-thread, the memory controller wasn't perfect yet. The 68030 can fill a cache line using a "burst" mechanism, where it takes advantage of the fact that reading consecutive memory locations is much faster than reading random locations.
I had implemented this "burst transfer" at a fairly early stage, but did not optimize it "to the max". A cache line of the 68030 consists of four longwords (32-bit words). If a memory location is not available in the cache, the CPU will try to read the whole cache line, starting from the location where it needs the next word. If the first access is at the start of a cache line, then words 0-1-2-3 are fetched at top speed from memory. If word #2 is required first, then the burst order is 2-3-0-1. Notice the wrap-around in the middle of the burst - this is essentially "going backwards in memory". Here's where statistics come into play: Usually, a program is executed "forward", so the previous words (in this case words #0 and #1) are "most probably" not required.
I have now managed to abort the burst transfer at the wrap-around stage, which gained roughly 1.5% speed. The ACA630-25 now cracks the 6-Mips-barrier, and if you want to examine the speed of the final 1230 cards, I have also attached AIBB modules of the two 1230 models.
We'll set up and program the assembly machines tomorrow, assembly is planned for monday. This is SMT assembly only - the THT assembly will have to wait until the PGA sockets have been delivered. After I got "way too many" offers with delivery time "A", and got a different delivery time "B" with B >> A, I was fed up with tricks like that and ordered my own tooling for PGA sockets. The good side about this is that we won't only have white PCBs and white A1200 connectors, but also white PGA sockets. Since the ACA630 will be "all black", I'll use my stock of black PGA sockets for those.