You can't add up MIPS that way. Faster CPU speed always means more memory waitstates - I'd have to use faster memory chips, which is NOT the plan for the A600 board.
It may happen that the 25MHz version is faster than a 33MHz version, because I'd have to insert waitstates to meet all timing parameters. There's a good 20 parameters that you may violate if you carelessly change the clock speed.
The A600 accelerator is equipped with 133MHz memory chips. Since I run them in CL=2 mode, the max. frequency is 100MHz. Since I don't do NOP commands between "row open" and "access", the max. allowed frequency is down to 50MHz, which is exactly my "frontside speed". Half of that goes to the CPU. Although it may sound weird, the 50MHz clock rate is pushing the 133MHz memory chips to the limit.