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Old 06 August 2010, 21:13   #105
old bearded fool

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Join Date: Jan 2010
Location: Bangkok
Age: 49
Posts: 337
Originally Posted by alexh View Post
Interested to know how you came to that? How did you guestimate how many gates are required for a synthesisable 68060 is considering the code doesn't exist yet? Or the gates in a real 68060 for that matter? You know those are not real gates and never map 1:1 to ASIC gates. Are you using the "25,000 LE's" number passed around of the as yet "imaginary" 68050 passed around the NatAmi website?
My guesstimate = TG68 requirement x 4

I did consider there are other things (other than clock rate) which can affect the performance of the CPU which an FPGA will be good at. For example much much bigger I & D caches, fewer clock cycles per instruction etc. so a lower target frequency might not result in a much slower processor. But there are also things in the 060 which will be difficult to implement 1:1 because of their complexity.
I agree, clock speed doesn't really mean much without more info. For example, if you can do an instruction that takes four clock cycles on a real 68060 and optimize it down to two or maybe one cycle in the FPGA. I think there's a lot to gain in optimization regarding memory handling (with the memory controller primitive for Spartan 6 in mind).

I guess this is just going to have to be a suck-it-and-see exercise where someone will have to code up something agree it is comparable technology and run it through the tools.

If the NatAmi team really do have any code for this 050 are they making it open source development?
I haven't been following NatAmi project much, just know it's been going on for a long time.
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