Originally Posted by modrobert
Then I just picked one which seemed to have enough logic cells (gates) to fit 68060 based on this table
Interested to know how you came to that? How did you guesstimate how many gates are required for a synthesisable 68060 is considering the code doesn't exist yet? Or the gates in a real 68060 for that matter? You know those are not real gates and never map 1:1 to ASIC gates. Are you using the "25,000 LE's" number passed around of the as yet "imaginary" 68050 passed around the NatAmi website?
I did consider there are other things (other than clock rate) which can affect the performance of the CPU which an FPGA will be good at. For example much much bigger I & D caches, fewer clock cycles per instruction etc. so a lower target frequency might not result in a much slower processor. But there are also things in the 060 which will be difficult to implement 1:1 because of their complexity.
I guess this is just going to have to be a suck-it-and-see exercise where someone will have to code up something agree it is comparable technology and run it through the tools.
If the NatAmi team really do have any code for this 050 are they making it open source development?