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Old 20 June 2008, 20:19   #135
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Join Date: Dec 2007
Location: Bath, UK
Posts: 119
Originally Posted by alexh View Post
Marketing bull.

But if you are prepared to take the risk (or you have a relatively flat synchronous design with few clocks and no speed bridges) then yes, you can get better clock rates from a hardened FPGA.
How is that marketing bull? They said 'up to twice the core logic performance', they did not promise that it would offer that increase every time.

In any case, if the HardCopy relied on snake oil hype they shouldn't have survived long enough to get to their fourth version of the technology, would they?
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