More to add:
If the Natami consumer edition had an integrated CPU in the graphics chipset (as is currently planned) then they could optimize out problems with interrupts that would have previously caused pipeline stalls and cache dumps such as video beam synchronization interrupts. The PowerPC does something similar with the built-in clock for its interrupt controller on the CPU. They could also add other optimizations such as adding opcodes to prefetch linked list nodes so that blit nodes would be cached in the hardware. The list is almost endless!