Originally Posted by gizmomelb
Alexh, I could be wrong
You're not wrong but then again I dont know anyone who ever uses the Analog extension to Verilog (called AMS)
Verilog and VHDL are both high level description languages and can be used to describe anything, although they are mainly used for digital and behavioural logic.
Synthesisers exist for both which convert from the high level language to digital electronic gates.
Verilog is a European creation but is mainly used in the USA, and VHDL was created by Americans and is mainly used in Europe.
Verilog is very much like C in it's syntax. Very easy to learn and write code but due to it's flexibility it is also very easy to make accidental functional errors which are not syntactic errors.
VHDL is very much type based, very intricate and explicit language. It is MUCH harder to accidentally create a functional error which is syntactically correct.
Verilog is used regularly to describe netlists (low level post synthesis structures) whereas VHDL is not usually. This is mainly from the fact that the synthesis tools were written by Americans and was adopted as the industry standard.
Analog is seldom (never?) designed in HDL, I think that the analog extension (Verilog-AMS) may be used in simulations, but to be honest I find the whole area "Magical".
Analog is usually are done in a mixture of schematic and full custom layer design almost like a "paint" package for chips. A bit of metal here, a bit of Polysilicon there etc.