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girv · 20 December 2004, 12:11

FYI, from: http://www.go-ecs.com/cold/coldtek1.htm

Some differences between 68k and ColdFire

The ColdFire family has a 68k heritage, but the processors are not drop in replacements for 68k processors. Some of the differences are explained below.

Register Model

ColdFire retains the 68k's set of sixteen 32-bit registers (8 data registers, named D0-D7, and 8 address registers, named A0-A7). There are a couple of small differences, however.

Stack Pointer
Most 68k processors switch from a user stack pointer (A7, aka USP) to a supervisor stack pointer (A7', aka SSP) when the processor transitions into supervisor mode. Some 68k processors support a third stack pointer register for interrupts, named the Interrupt Stack Pointer (ISP). In contrast, the ColdFire family supports a single stack pointer (A7) across its operating modes. Vector Base Register
Most 68k processors allow the user to locate the vector table practically anywhere in memory via the Vector Base Register (VBR) . With ColdFire, the VBR still exists, but only the upper 12 bits are meaningful (which implies the vector table is always on a 1 Mbyte boundary, since the lower 20 bits are treated as zero.)

Instruction Set and Addressing Modes
ColdFire and 68k use 16-bit words (32-bit values are referred to as longwords.)

68k instructions can be as many as eleven words (a 16-bit opcode, and up to 10 extension words specifying operands). On the other hand, ColdFire instructions are either 1, 2 or 3 words long. Not all 68k instructions are supported under ColdFire; some of the more complicated and less-used 68k instructions have been eliminated.

One of the implications of a smaller instruction size is reduced addressing mode capabilities. 68k instructions offer some very elaborate addressing modes which result in dense code. For example, a single 68k instruction can move an 8, 16 or 32-bit value between any two 32-bit memory addresses without any intermediate transfers to registers. Of course, the instruction requires 1 word for the opcode and 4 additional words for the two 32-bit addresses.

Consult Motorola's documentation for complete information on instructions and addressing modes offered by ColdFire. Most 68k code can be ported to ColdFire with minimum effortl. The more intricate areas (MMU and cache manipulation, special processor-specific registers, etc...) still require human intervention, especially when there is no equivalent register or operation on ColdFire.

Exception Processing

The 68k's exception processing microcode builds an exception stack frame for each exception taken; the size and contents of the stack frame depends on the exception. With ColdFire, all exceptions build the same size stack frame. Also, the ColdFire will force the stack to 4-byte alignment (if it isn't already) prior to building the stack frame; information within the stack frame indicates how much padding (if any) was introduced to force the alignment. Upon return from exception, the ColdFire microcode restores the stack pointer to its previous value, accounting for padding as well.

Also, the ColdFire exception types are a subset of the exception types defined for the 68k family. 68k exceptions that are no longer supported are marked as "reserved" in the ColdFire exception table.

20 December 2004, 12:11	#20
girv Mostly Harmless Join Date: Aug 2004 Location: Northern Ireland Posts: 1,133	FYI, from: http://www.go-ecs.com/cold/coldtek1.htm Some differences between 68k and ColdFire The ColdFire family has a 68k heritage, but the processors are not drop in replacements for 68k processors. Some of the differences are explained below. Register Model ColdFire retains the 68k's set of sixteen 32-bit registers (8 data registers, named D0-D7, and 8 address registers, named A0-A7). There are a couple of small differences, however. Stack Pointer Most 68k processors switch from a user stack pointer (A7, aka USP) to a supervisor stack pointer (A7', aka SSP) when the processor transitions into supervisor mode. Some 68k processors support a third stack pointer register for interrupts, named the Interrupt Stack Pointer (ISP). In contrast, the ColdFire family supports a single stack pointer (A7) across its operating modes. Vector Base Register Most 68k processors allow the user to locate the vector table practically anywhere in memory via the Vector Base Register (VBR) . With ColdFire, the VBR still exists, but only the upper 12 bits are meaningful (which implies the vector table is always on a 1 Mbyte boundary, since the lower 20 bits are treated as zero.) Instruction Set and Addressing Modes ColdFire and 68k use 16-bit words (32-bit values are referred to as longwords.) 68k instructions can be as many as eleven words (a 16-bit opcode, and up to 10 extension words specifying operands). On the other hand, ColdFire instructions are either 1, 2 or 3 words long. Not all 68k instructions are supported under ColdFire; some of the more complicated and less-used 68k instructions have been eliminated. One of the implications of a smaller instruction size is reduced addressing mode capabilities. 68k instructions offer some very elaborate addressing modes which result in dense code. For example, a single 68k instruction can move an 8, 16 or 32-bit value between any two 32-bit memory addresses without any intermediate transfers to registers. Of course, the instruction requires 1 word for the opcode and 4 additional words for the two 32-bit addresses. Consult Motorola's documentation for complete information on instructions and addressing modes offered by ColdFire. Most 68k code can be ported to ColdFire with minimum effortl. The more intricate areas (MMU and cache manipulation, special processor-specific registers, etc...) still require human intervention, especially when there is no equivalent register or operation on ColdFire. Exception Processing The 68k's exception processing microcode builds an exception stack frame for each exception taken; the size and contents of the stack frame depends on the exception. With ColdFire, all exceptions build the same size stack frame. Also, the ColdFire will force the stack to 4-byte alignment (if it isn't already) prior to building the stack frame; information within the stack frame indicates how much padding (if any) was introduced to force the alignment. Upon return from exception, the ColdFire microcode restores the stack pointer to its previous value, accounting for padding as well. Also, the ColdFire exception types are a subset of the exception types defined for the 68k family. 68k exceptions that are no longer supported are marked as "reserved" in the ColdFire exception table.