Quote:
Originally Posted by Rotareneg
...but now the loading screens are glitchy:
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When looking at the glitching in the visual debugger, I can see that on hpos cycle 0, CPU cycles are able to steal the bitplane DMA on cycle 0, and sometimes I've also seen a refresh cycle conflict that messes up the DMA for the rest of the line.
I have no idea how the "estimated cycles" code works, but this new line in beta 6 seems to be the culprit:
Code:
ecycs = maxhposeven ? estimated_cycles_buf0 : estimated_cycles_buf1;