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Rst7 · 10 February 2023, 22:11

From my point of view, if we consider the execution of code from the cache, then the behavior of simple instructions in 68020 is quite clear:

1. The source address is calculated.
2. The start of the reading cycle occurs at the last cycle of calculating the source address. This last cycle corresponds to a read cycle while no AS is set yet.
Apparently, the address has already been calculated by this time (i.e. the real calculation takes one cycle less than the specified "Fetch Effective Address").
3. While the read cycle is in progress, the calculation of the destination address is started, if necessary.
4. After the end of the read cycle, execution starts (for example, add will take 2 cycles).
5. One cycle before the end of the execution, the recording cycle starts.

The move instruction seems to have some kind of fast path within the 68020 because its data is ready one cycle early. For example move (a0),(a0) takes 7 cycles and add d0,(a0) will take 4+4=8 cycles. Although both of these instructions are equivalent in terms of the number of memory access cycles, the second instruction will have an empty clock in bus activity between read and write.

Code:

move (a0),(a0):

1234567
AS.....
.RRR...
..AD...
....PP.
....WWW
......next instruction

AS - calculate source EA
RRR - read memory
AD - calculate destination EA
PP - perform
WWW - write memory


add d0,(a0):

12345678
AS......
.RRR....
.....WWW
....PP..
......next instruction


move d0,(a0):

1234
AD..
.WWW
PP..
..next instruction


move (a0),d0:

123456
AD....
.RRR..
....PP
......next instruction


lsl #1,(a0):

123456789
AD.......
.RRR.....
....PPP..
......WWW
.......next instruction

And most importantly, what I wanted to convey in the first post:

The PP stage cannot start executing before the RRR stage has completed (with all wait states), but WinUAE behavior looks different.

10 February 2023, 22:11	#12
Rst7 Registered User Join Date: Jan 2022 Location: Kharkiv Posts: 48	From my point of view, if we consider the execution of code from the cache, then the behavior of simple instructions in 68020 is quite clear: 1. The source address is calculated. 2. The start of the reading cycle occurs at the last cycle of calculating the source address. This last cycle corresponds to a read cycle while no AS is set yet. Apparently, the address has already been calculated by this time (i.e. the real calculation takes one cycle less than the specified "Fetch Effective Address"). 3. While the read cycle is in progress, the calculation of the destination address is started, if necessary. 4. After the end of the read cycle, execution starts (for example, add will take 2 cycles). 5. One cycle before the end of the execution, the recording cycle starts. The move instruction seems to have some kind of fast path within the 68020 because its data is ready one cycle early. For example move (a0),(a0) takes 7 cycles and add d0,(a0) will take 4+4=8 cycles. Although both of these instructions are equivalent in terms of the number of memory access cycles, the second instruction will have an empty clock in bus activity between read and write. Code: move (a0),(a0): 1234567 AS..... .RRR... ..AD... ....PP. ....WWW ......next instruction AS - calculate source EA RRR - read memory AD - calculate destination EA PP - perform WWW - write memory add d0,(a0): 12345678 AS...... .RRR.... .....WWW ....PP.. ......next instruction move d0,(a0): 1234 AD.. .WWW PP.. ..next instruction move (a0),d0: 123456 AD.... .RRR.. ....PP ......next instruction lsl #1,(a0): 123456789 AD....... .RRR..... ....PPP.. ......WWW .......next instruction And most importantly, what I wanted to convey in the first post: The PP stage cannot start executing before the RRR stage has completed (with all wait states), but WinUAE behavior looks different.